Electrostatic discharge circuit for high speed, high voltage circuitry
US5473500A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Jan 13, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node. The first controlled path is from the signal node to V.sub.cc via the source and drain electrodes of a first transistor. The gate of the transistor is at a soft ground by connection of the gate through a resistor and an inverter to a fixed voltage supply potential (V.sub.cc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second and third transistors to ground. The second transistor has a gate tied at V.sub.cc by means of a resistor and inverter to ground. The third transistor is at soft ground by means of a resistor and inverter to V.sub.cc. The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor. The protection circuit may include a third controlled path through a fourth transistor, if low voltage circuitry is tied to the signal node. The fourth transistor includes a gate that is tied high by connection of the gate to ground via…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.