Method for generating hardware description of multiplier and/or multiplier-adder
US5473558A · kind A · utility
2Cited by
2References
6Claims
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Assignee
Inventor
Key dates
| Filing date | Jan 21, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Jan 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a hardware description of a multiplier/multiplier-adder for integrating a signal processing circuit includes the steps of acquiring input parameters such as a word length of multiplier factor, generating a first hardware description of a first add for adding partial products and an inputs addend, determining a redundancy index r by using the input parameters, generating a second hardware description of a second add circuit for performing a carry-add of every r bits of the output of the first add circuit, and replacing useless circuits from the hardware descriptions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.