BICMOS cache TAG having ECL reduction circuit with CMOS output
US5473561A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Sep 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache TAG RAM (25) includes a reduction circuit (39) for comparing match signals from a plurality of exclusive OR logic circuits (33, 34) and provides a hit signal when all of the TAG address bits of a stored TAG address is the same as input address bits. The reduction circuit (39) provides a miss signal when any one or more of the bits of the stored TAG address is not the same as the corresponding bits of the input address bits. In one embodiment, the reduction circuit (39) uses a plurality of transistors (77, 78) coupled to a conductor (75) for discharging the conductor (75) if one of the exclusive OR logic circuits (33, 34) indicates a miss. In another embodiment, the reduction circuit (39") charges the conductor. The comparison can be made using signals having small signal swing at high speed, and a reference voltage is not needed for the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.