Multi-port static random access memory with fast write-thru scheme

US5473574A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Rainer Clemen · Böblingen, DE
• Klaus J. Getzlaff · Schenefeld, DE

Key dates

• Filing date: Feb 5, 1993
• Grant date: Dec 5, 1995
• Expiry date: Feb 5, 2013

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C8/16
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A fast write-thru scheme is proposed for use in a multi-port static random access memory. This is achieved by operating the read and write ports of the SRAM circuitry in two separate but interleaved stages. In a first stage, a write path is set up comprising a write address decoder, an AND gate connected to a clock signal, the AND gate enabling a write port coupled to the latch of a memory cell. In the second stage, a read path is set up comprising a read address decoder selecting a read port, through which data is read from the cell latch to a data out buffer. To minimize the write-thru access time, the synchronous read path controlled by the read address is interleaved with the write path triggered by a write clock (CE), so that the read address is delayed with respect to the clock and the write addresses. Thus the write-thru access time becomes independent from the write time needed for overwriting the multi-port SRAM cell and equal to the read address access time achieved in a fully static or synchronous read operation.