Serial memory
US5473577A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Mar 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/103
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a serial memory which internally converts serial input data into parallel data and writes the data into a memory array two or more bits at a time, and which reads data two or more bits at a time from the memory array and internally converts the read data into serial data for output, circuits are provided that allow selective reversing of the order of parallel conversion on the serial input data and of serial conversion on the parallel data read from the memory array. This serial memory is also provided with a memory controller to reverse the ascending or descending order of the access address for the memory array in the read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.