Counter and/or divider arrangement
US5473652A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Mar 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A counter and/or divider arrangement, comprising at least two subsidiary counter circuits, each of which comprises a number of flipflops which are concatenated in respect of their data inputs and outputs, all subsidiary counter circuits receiving a common clock signal, and also comprising at least one logic element, enables the implementation of arbitrary counting operations or division ratios with a low expenditure as regards circuitry and with low-noise operation in that in each logic element signals from the data output of one of the flipflops of at least a part of the subsidiary counter circuits are combined in conformity with an AND-function so as to form an associated resultant signal, each of the resultant signals being applied to at least one of the subsidiary counter circuits as a reset signal in order to switch the subsidiary circuit to an initial state, an output signal being formed from at least one of the resultant signals, the product of the total numbers of flipflops of all subsidiary counter circuits being larger than or equal to a predetermined maximum count or division ratio, the total numbers being determined so that they do not exhibit common prime factors, the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.