Fault isolation circuit
US5473752A · kind A · utility
10Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 20, 1995 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Jan 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for detecting and isolating faults in a two-wire communications loop which includes a number of node circuits dispersed along the loop. Each node circuit executes a fault detection algorithm and selectively switches its connections to adjacent node circuits to effectively isolate itself from the fault condition. When all node circuits have completed their respective fault detection algorithms the fault condition is disconnected from the two-wire communications loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.