I/O controller using single data lines for slot enable/interrupt signals and specific circuit for distinguishing between the signals thereof
US5473757A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 1992 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Dec 11, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic controller is provided in which I/O modules situated in respective slots are coupled to a CPU by a main bus including a serial data line. A dedicated slot enable line is provided from the CPU interrupt controller to each slot into which an I/O module may be positioned. In this manner, the CPU can enable a selected I/O module when desired. The I/O module includes an interrupt feature wherein an interrupt signal is provided to the same slot enable line which communicates a slot enable signal to the I/O module. The I/O module returns an interrupt on the slot enable line at times other than when the slot enable line is being used by the CPU interrupt controller to send a slot enable signal. The CPU interrupt controller includes an interrupt detection circuit which makes a determination of when two conditions simultaneously occur, namely when both a particular slot enable line is active and the CPU is not enabling the corresponding slot with the slot enable signal. The simultaneous occurrence of these conditions indicates that an interrupt is being received from the I/O module coupled to that slot enable line. By employing this apparatus and technique, the slot enab…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.