Clock generator
US5473768A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Feb 23, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selector 11 selects one of a plurality of reference clock signals based upon a selection signal. A hardware reset signal 103 is delayed by a predetermined time. The selection signal is sent to the selector responsive to a set signal. The sending of the selection signal is stopped responsive to the delayed hardware reset signal. The set signal is delayed by a predetermined time. A first flip-flop 13 is set in response to the hardware reset signal or a software reset signal, is supplied with the delayed set signal as a count input, and is supplied with low level as a data input. A second flip-flop 16 receives a logic AND signal of an output signal from the selector 11 and the hardware reset signal as a count input and receives a logic OR signal of the output of the first flip-flop 13 and an inverted output of the second flip-flop 16 as a count signal, and generates a clock output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.