Notched insulation gate static induction transistor integrated circuit
US5475242A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1995 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | Apr 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.