Data processing with a self-timed approach to spurious transitions
US5475320A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 1994 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | Aug 11, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital electronic device includes a digital circuit responsive to a logic transition at an input thereof to produce at an output thereof a spurious logic transition ultimately followed by a stable logic level. A transition detector produces a detection signal in response to the logic transition at the digital circuit input, the transition detector including a latch circuit having an output for producing the detection signal. A self-timed circuit receives the detection signal and, after delaying for a suitable time, produces a done signal. A switching circuit is responsive to the done signal to connect the digital circuit output to a selected logic node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.