Method of target generation for multilevel hierarchical circuit designs
US5475607A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1994 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | Apr 12, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generating delay targets for creating a multilevel hierarchical circuit design by providing a hierarchical design description and delay constraints of the circuit design; generating a net measure for each net and macro cell of the circuit design, and generating an abstract delay model for each macro cell of the circuit design based on the design description, wherein net measure is the estimated resistive-capacitive delay of a net derived from the estimated length of the net based on area-driven design, and an abstract delay model is a description of delays through a macro cell; generating delay targets for the nets and macro cells based on the net measures, the abstract delay models and the delay constraints; and creating the circuit design based on the delay targets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.