Heuristic digital processor using non-linear transformation
US5475793A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1994 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | May 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a non-linear function to produce training .phi. vectors. A systolic array arranged for QR decomposition and least means squares processing forms combinations of the elements of each .phi. vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed test data to provide estimates of unknown results. The processor is applicable to provide estimated results for problems which are non-linear and for which explicit mathematical formalisms are unknown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.