Multistate microprocessor bus arbitration signals
US5475850A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 1993 |
| Grant date | Dec 12, 1995 |
| Priority date | — |
| Expiry date | Jun 21, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor bus arbitration communications scheme for enhancing efficiency and performance of a multi-master bus system, typically within a computer system, including a central processing unit ("CPU") being a primary bus master, a bus arbiter and at least one alternative bus master coupled together by a bus. The CPU includes an internal memory element, a bus queue and bus control logic which collectively operate to generate a plurality of microprocessor bus arbitration signals to the bus arbiter. These microprocessor bus arbitration signals include a first bus arbitration signal indicating whether the CPU requires access to the bus and a second bus arbitration signal indicating that the CPU requires immediate access to the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.