Semiconductor structure using local planarization with self-aligned transistors
US5477074A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 22, 1994 |
| Grant date | Dec 19, 1995 |
| Priority date | — |
| Expiry date | Aug 22, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/133
- WIPO fieldMaterials, metallurgy
- WIPO sectorChemistry
Abstract
A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer and underlying oxide layer are removed only in the area of the buried contact, while an overlying metal or polysilicon conductive layer contacts the upper surface of certain of the transistor gate structures, the topside insulating layer of which has been removed for this purpose.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.