Logic circuit with negative differential resistance device
US5477169A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 1994 |
| Grant date | Dec 19, 1995 |
| Priority date | — |
| Expiry date | Jun 20, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit including a pair of FETs connected in parallel and including first and second common current terminals, each of the FETs further having a control terminal connected to receive a logic signal thereon. A negative differential resistance device affixed to one of the first and second common current terminals and having a conductance characteristic such that the device operates at a peak current when one of the FETs is turned ON and at a valley current when both of the FETs are simultaneously turned ON. A load resistance coupled to the other of the first and second common current terminals and providing an output for the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.