Ultra low power gain circuit (UGC)
US5477173A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1993 |
| Grant date | Dec 19, 1995 |
| Priority date | — |
| Expiry date | Jul 30, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/687
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An ultra low power gain circuit (UGC) implements a unique operational mode of a source follower circuit, and enables programmable gains greater than unity. A MOSFET has a gate terminal coupled to an input capacitance (Cin). A potential at a drain of the MOSFET is clocked to enable charge to flow through the channel. This charge charges a capacitor (Cout) that is connected to a source of the MOSFET. After charging Cout, the drain potential is restored to an initial value, and the charge on Cout discharges back through the MOSFET until the source voltage is one threshold drop from the gate potential, at which time the MOSFET turns off. Cout then stops discharging, and the final voltage appearing on Cout is a function of the magnitude of the gate voltage appearing on Cin. As the voltage at the source of the MOSFET changes, capacitive coupling, via (Cgs) to the gate, causes the gate voltage to also change. The value of the gate voltage determines a magnitude of a final voltage to which the source settles. A feedback effect is thereby produced which influences the voltage transfer function of the MOSFET. A minimum voltage gain is unity. However, through a selection of capacitor values f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.