Monolithically integrated semiconductor arrangement with a cover electrode
US5479046A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 1994 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Jun 22, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
The invention relates to a monolithically integrated semiconductor arrangement, where from the first main surface a first zone (p) and a second zone (n.sup.+) are diffused into a substrate (2), which is weakly doped (substrate region n.sup.-) under a first main surface (3) and is more strongly doped (substrate region n.sup.+) under a second main surface (4). An insulating passivation layer is attached to the first main surface (3), on top of which a metallic cover electrode (D) is located, which covers adjacent substrate regions (n.sup.-) and the edge areas of the first zone (p) and the second zone (n.sup.+). In accordance with the invention, at least one additional zone (.nu.) of the same type of conductivity as the associated zone (n.sup.+), but with weaker doping, is diffused in for increasing the break-through voltage, and is connected to the zone (n.sup.+), does not contact the other zone (p) and prevents the zone (n.sup.+) from directly bordering the substrate (n.sup.-) underneath the cover electrode (D).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.