Logic gate with matched output rise and fall times and method of construction
US5479112A · kind A · utility
15Cited by
6References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1995 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Apr 19, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic gate with highly matched output rise and fall times is provided which includes at least one stacked transistor pair (24) and at least one complementary stacked transistor pair (30) connected in parallel across at least one node (NODE 1 and NODE 2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.