Slew rate controller for high speed bus
US5479124A · kind A · utility
42Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1993 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Aug 20, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique for high speed transmission of digital signals on a bus line with reduced signal ringing, bounce and bus contention current. The approach uses a multi-partitioned driver design with temporary and steady state parts incorporating internal feedback and delay techniques to control the output slew rate. A built-in function outputs the driving status of the transceiver and allows the output to enter the high impedance status asynchronously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.