Frequency multiplying clock signal generator
US5479125A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 1994 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | May 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal generator for creating an output clock signal with fifty percent duty cycle and multiple of the input clock signal frequency allows generation of such a signal independent of input signal frequency and duty cycle. The generator utilizes an adjustable-delay oscillating feedback loop. A serial array of propagating delay elements measure the period of the input clock signal by triggering on successive input clock signal leading edges. This propagation lengthens the oscillating feedback loop until the output signal matches the desired frequency multiple. The feedback loop automatically adjusts according to a predetermined fraction of the period of the input clock signal. A fixed ratio of feedback loop delay to serial array delay ensures an output signal with a desired frequency multiple of the input signal frequency. Incorporation of an inverting logic gate in the oscillating feedback loop ensures a half-wave output clock signal having a fifty percent duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.