Programmable digital signal processor using switchable unit-delays for optimal hardware allocation
US5479363A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1993 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Apr 30, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0294
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel switchable unit-delay has been developed for the efficient implementation of programmable digital finite impulse response filters and correlators. A p-tap consisting of this novel switchable unit-delay and a two-non-zero-digit partial product generator and adder have been implemented. The combination of several p-taps, made possible by the switchable unit-delay, allows for the efficient implementation of coefficients with more than two non-zero digits. In a straightforward implementation of a programmable finite impulse response filter, many tap "multipliers" would significantly waste valuable computational resources since all filter taps would need to accommodate "difficult" coefficient values (i.e., many non-zero digits), while for any specific transfer function, most filter taps would not require such extreme capabilities. The switchable unit-delay not only allows the programing of the number of taps and the specific tap-coefficient values, it provides the capability for programing the optimal allocation of hardware resources to each filter tap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.