Method for testing large memory arrays during system initialization
US5479413A · kind A · utility
16Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1994 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Jun 6, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method for testing a large memory array of a digital computer system during system initialization or reset. First, the memory test method checks the whole memory array for addressing faults, and then a first portion of the memory array for both address line and data failures. While operational firmware is loaded into and begins to execute from the tested first portion, the remaining address locations of the array are tested in a background task. Beginning at the last address of the first portion, sequential portions of memory array are tested and released to the functional code as they have been tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.