Virtual address translation hardware assist circuit and method
US5479628A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 1993 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Oct 12, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, and circuitry that operates in accordance with the method, for generating an entry for a translation buffer in a data processor that employs virtual memory addressing. The method includes the first steps of storing a Faulted Virtual Address in a first register (96) and a Zone Table Address (ZTA) in a second register (94). In response to the execution of a micro-instruction, a next step forms an address in memory of a Zone Table Entry (ZTE) by selectively combining a first portion of the content of the first register with the content of the second register, while simultaneously testing the ZTA for physical address mapping. In response to an execution of a next micro-instruction, a next step accesses the ZTE with the formed address, and forms an address in memory of a Segment Table Entry (STE) by selectively combining a second portion the content of the first register with a content of the ZTE, while simultaneously testing the ZTE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the STE with the formed address, and forms an address in memory of a Page Table Entry (PTE) by selectively combining a third portion of the content of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.