Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking
US5479641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1993 |
| Grant date | Dec 26, 1995 |
| Priority date | — |
| Expiry date | Mar 24, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array, a status array, and a data array. Parity information is generated and checked to verify data and tag integrity. The parity field is stored in a status array physically separate from the tag array. The status array is offset in timing so that it lags behind the tag array for both read and write operations. Therefore, fields in the status array can be written in the early part of the next clock cycle without affecting the tag array or another operation that may be scheduled for the next time cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.