Clock distribution and control in an integrated circuit
US5481209A · kind A · utility
17Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1993 |
| Grant date | Jan 2, 1996 |
| Priority date | — |
| Expiry date | Sep 20, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for improved clock distribution and control in an integrated circuit which minimizes clock skew between various parts of the integrated circuit chip. Clock loads are evenly distributed between tributaries. Capacitive loading is utilized to balance any differences between tributaries and for minimizing clock skew throughout the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.