Method for controlling clock frequency of a digital logic semiconductor according to temperature
US5481210A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 1994 |
| Grant date | Jan 2, 1996 |
| Priority date | — |
| Expiry date | Nov 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a digital logic semiconductor component, wherein: the logic semiconductor component is operated in several operational modes at respective fixed clock cycles depending on environmental temperatures; each operational mode is allocated a respective clock cycle with, in each case, a different clock frequency; each operational mode is allocated a respective temperature-dependent limit value with, in each case, a different limit temperature which when reached causes a change of operational mode to occur; and, when changing to an operational mode with a higher limit temperature, the clock frequency is reduced, and when changing to an operational mode with a lower limit temperature, the clock frequency is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.