Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories
US5481500A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1994 |
| Grant date | Jan 2, 1996 |
| Priority date | — |
| Expiry date | Jul 22, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.