Dedicated processor for task I/O and memory management
US5481707A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1995 |
| Grant date | Jan 2, 1996 |
| Priority date | — |
| Expiry date | Apr 11, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system performs memory to memory transfer, task scheduling and I/O request handling via a group of dedicated processors (e.g. a memory interface unit, an I/O unit, a data transfer unit, and a task control unit). The memory interface unit facilitates data interaction between the memory and the remainder of the system. The I/O unit is coupled to the memory interface unit and performs high level I/O job functions including I/O job scheduling, I/O job path selection, gathering of job statistics and device management. The data transfer unit is coupled to the memory interface unit and moves data between memory locations. The task control unit, coupled to the memory interface unit, allocates and deallocates events, maintains the status of tasks running on the system and schedules the execution of tasks. A hierarchical error reporting scheme is used by all of the processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.