Bus control for a plurality of digital signal processors connected to a common memory
US5481727A · kind A · utility
17Cited by
22References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1993 |
| Grant date | Jan 2, 1996 |
| Priority date | — |
| Expiry date | Nov 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) connected in parallel, each DMM having a DSP, a local memory and an interrupt control unit, a plurality of common memories for storing data which is being processed, parameters, etc., an input frame memory which enables reading and writing operations to be executed asynchronously, a combination of a task control unit and a task table for distributing tasks to the DMM's, a plurality of independent common buses, and a combination of a bus control unit and a bus control table for bus sharing control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.