Data and clock recovery circuit
US5483180A · kind A · utility
Inventors
Key dates
| Filing date | Nov 22, 1994 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | Nov 22, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a data and clock recovery circuit possible to restore data signals and synchronizing clocks which have been distorted during transmission over the communication line, which is comprised of the following: main oscillation loop that maintains operating frequency by using the input data and a self oscillation loop that operates using reference clock embedded within multiplex communication devices when communication lines get shorted or when power is restored after an outage; loop selecting switch which selects the main oscillation loop during normal operating mode and selects the self oscillation loop when communication line shorts or when the power is being restored; data signal monitor which connects to the loop selecting switch and determines communication line shorting by monitoring data transmission; power supply monitor which connects to the loop selecting switch and monitors the restoration of power after an outage. The circuit maintains stable operation and supplies stable output to multiplex communication devices not only during the normal operating conditions, but also when there is a communication line shorting or restoration of power after a power supply outag…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.