Semiconductor memory device having bidirectional potential barrier switching element
US5483482A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1992 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | Mar 17, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a plurality of memory cells each including an element with a potential barrier serving as a switching element and a capacitor one terminal of which is connected to the switching element. The memory cells are disposed in a matrix arrangement. Terminals of the respective capacitors which are not connected to the switching elements are connected to each other in intersection with bit lines in the memory cell arrangement to thereby form word lines. Alternatively, the terminals of the respective capacitors connected to the switching elements may be connected to each other in intersection with the bit lines to thereby form word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.