Bus system for use with information processing apparatus
US5483642A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1994 |
| Grant date | Jan 9, 1996 |
| Priority date | — |
| Expiry date | Sep 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.