Semiconductor memory device having redundant column and operation method thereof
US5485425A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 20, 1995 |
| Grant date | Jan 16, 1996 |
| Priority date | — |
| Expiry date | Jan 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a semiconductor memory device having a redundant column. This memory device has a redundant column disposed in the direction of the Y-system address, a ROM accessed by using an X-system address, a Y-system address signal having a defective cell included in the cells therein being electrically written into the ROM, a comparator circuit for comparing a signal read out from this ROM with a Y-system address signal and outputting a coincidence signal upon coincidence, and a defect relieving circuit responsive to output of the coincidence signal from this comparator circuit to cause selection of the redundant column of Y system instead of the Y-system address selection device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.