Apparatus for simulating a stack structure using a single register and a counter to provide transmit status in a programmed I/O ethernet adapter with early interrupts
US5485584A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 1995 |
| Grant date | Jan 16, 1996 |
| Priority date | — |
| Expiry date | Jan 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40032
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.