Data structure access control circuit and method utilizing tag bits indicating address match and memory fullness conditions
US5485593A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 1994 |
| Grant date | Jan 16, 1996 |
| Priority date | — |
| Expiry date | Mar 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17368
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit utilizing first and second tag bits for granting access to a block of memory in a multiprocessor system having a shared memory are provided. When a memory request for exclusive access to a block of memory is granted, the starting address for that block of memory is placed in a register bank, thereby opening a semaphore. The starting address of a memory block of a subsequent memory access request is compared with the starting addresses corresponding to open semaphores within the register bank and access is denied to the requested block of memory if a match is found. The starting address associated with a request which is denied access is placed in a temporary buffer and the request is later granted access after the corresponding open semaphore becomes closed. A request which is granted memory access to a memory block which results in an open semaphore, has exclusive access to that block of memory until the semaphore is closed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.