High-speed staged decoder/quantizer
US5487075A · kind A · utility
1Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 1994 |
| Grant date | Jan 23, 1996 |
| Priority date | — |
| Expiry date | May 20, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4169
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A symbol-level pipelined structure for parallel systolic decoding of block codes which is a layered processor structure including a number of layers equal to the code length and each layer is adapted to decode the component codes of a concatenated code in sequence. The structure described provides efficient high rate decoding operation with an associated low cost and low hardware complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.