Digital interface circuit with dual switching points for increased speed
US5488322A · kind A · utility
Inventor
Key dates
| Filing date | Aug 29, 1994 |
| Grant date | Jan 30, 1996 |
| Priority date | — |
| Expiry date | Aug 29, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer, driver, or level-shifting circuit having an input connected to signal inputs of a pair of comparators and an output connected between a pair of pull-up and pull-down transistors controlled by the comparators. A first reference voltage applied to the reference input of the comparator controlling the pull-up transistor is selected to be less than the nominal transition point of the circuit, while a second reference voltage applied to the reference input of the comparator controlling the pull-down transistor is selected to be greater than the nominal transition point of the circuit, thereby allowing the circuit to recognize the beginning of signal transitions on the its input sooner. The comparators are differential amplifiers which are enableable and disableable in response to a feedback signal from the circuit's output in order to reduce current consumption during transitions. When the output is high, the comparator controlling pull-down is enabled, while the comparator controlling pull-up is disabled. When the output is low, the comparator controlling pull-up is enabled, while the comparator controlling pull-down is disabled. Undershoot and overshoot control circuitry may…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.