Method and apparatus for erasing an array of electrically erasable programmable read only memory cells
US5488586A · kind A · utility
14Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1994 |
| Grant date | Jan 30, 1996 |
| Priority date | — |
| Expiry date | Oct 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method of erasing memory cells while preventing overerasure of the memory cells is disclosed. By applying a large voltage across the floating gate of the memory cells, charge is removed from the floating gate. Once sufficient charge is removed from the floating gates of the memory cells to render them erased, a stop transistor halts the erasure process, thus preventing the overerasure of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.