Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
US5488729A · kind A · utility
103Cited by
15References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 7, 1994 |
| Grant date | Jan 30, 1996 |
| Priority date | — |
| Expiry date | Mar 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.