Semiconductor circuit having improved layout pattern

US5489860A · kind A · utility

Assignee

• FUJITSU LIMITED · JP

Inventors

• Masaya Kitagawa · Kawasaki, JP
• Shigeru Fujii · Shizuoka, JP

Key dates

• Filing date: Oct 20, 1993
• Grant date: Feb 6, 1996
• Expiry date: Oct 20, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/907

Abstract

A semiconductor circuit includes a plurality of first power supply lines which are arranged parallel to each other, a plurality of second power supply lines which are arranged parallel to each other and supplying a power supply voltage different from that supplied by the first power supply lines, where the first and second power supply lines run parallel to each other in a first direction, a first cell made up of the same number of first p-channel transistors and first n-channel transistors which are respectively coupled to the first and second power supply lines, where the first p-channel transistors and the first n-channel transistors are alternately arranged in a second direction and have the same size, and a second cell made up of a different number of second p-channel transistors and second n-channel transistors which are respectively coupled to the first and second power supply lines. The second p-channel transistors and the second n-channel transistors are alternately arranged in the second direction, and the second p-channel transistors are electrically coupled in parallel, so that the second p-channel transistors have a predetermined driving capability.