Voltage booster circuit
US5489870A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 1994 |
| Grant date | Feb 6, 1996 |
| Priority date | — |
| Expiry date | Mar 17, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/078
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A booster circuit which can cancel the back bias effect, can prevent the increase of the surface area of the circuit and the power consumption, prevent the complication of the clock generation circuit, and prevent lowering of the current capability, wherein a boosting stage is constituted by forming an nMOS transistor NT for carrying the charges and nMOS transistor NTB for transferring the voltage inside a p-well formed inside an n-well which is formed on a p-type semiconductor substrate and biased to a predetermined potential, constituted so that the source voltage of the nMOS transistor NT for carrying the charges which rise at the boosting is transferred via the nMOS transistor NTB for transferring the voltage to the substrate, that is, the p-well, whereby the back bias effect is suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.