Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation
US5490115A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1994 |
| Grant date | Feb 6, 1996 |
| Priority date | — |
| Expiry date | Jul 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer memory system incorporates a gang write circuit block to reduce the number of clock cycles required write a background pattern to memory cells during a memory test operation. The computer memory system includes (1) a two-dimensional array having multiple memory cells arranged in M rows and N columns and (2) the gang write circuit block for writing to N memory cells located in a row during one cycle and for writing to all of the memory cells in M cycles. The gang write circuit block may include two inverters for each column of the memory array and two test signals for the inverters. The background pattern may be all 1's, all 0's or some combination of 1's and 0's. The gang write circuit block becomes inactive during a normal read and write operation. When all the word lines of the computer memory system are selected, all the memory cells are written simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.