Semiconductor device including signal generating circuit with level converting function and with reduced area of occupation
US5490119A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 18, 1994 |
| Grant date | Feb 6, 1996 |
| Priority date | — |
| Expiry date | Apr 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.