Error correction system for n bits using error correcting code designed for fewer than n bits
US5490155A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1992 |
| Grant date | Feb 6, 1996 |
| Priority date | — |
| Expiry date | Oct 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes an error detection and correction system for detecting and correcting single-bit errors, two-adjacent-bit errors, and four-adjacent-bit errors. Two identical error detection and correction (EDC) circuits are connected to the system memory array, and each EDC circuit is connected to half of the data bits in alternating pairs. Each EDC circuit detects single-bit errors and two-adjacent-bit errors. The EDC circuits are connected to alternating pairs of data bits so that errors of up to four adjacent bits are actually detected and corrected, two bits by the first EDC circuit and two bits by the second. Thus, if one of the x4 DRAMs in a memory array fails, each erroneous data bit from the DRAM is corrected to its original value, and the failure of the DRAM is registered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.