Detecting false-locking and coherent digital demodulation using the same
US5490176A · kind A · utility
96Cited by
8References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1992 |
| Grant date | Feb 6, 1996 |
| Priority date | — |
| Expiry date | Oct 20, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a method of detecting false-locking the trains of clock signals corresponding to the two phase offset initially modulated trains of signals, the phase offset between said trains of clock signals is monitored, and false-locking is detected when the phase offset changes signal. Also, a method of demodulation implements this method of detecting false-locking. Also, a device for implementing the method of detecting false-locking contains a flip-flop in series with a monostable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.