Generally-diagonal mapping of address space for row/column organizer memories
US5490264A · kind A · utility
19Cited by
12References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1993 |
| Grant date | Feb 6, 1996 |
| Priority date | — |
| Expiry date | Sep 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a column conductor, and apparatus for addressing the flash array to produce such a generally-diagonal storage pattern. The arrangement allows the simplest forms of error detection and correction circuitry to be utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.