Method for manufacturing a capacitor structure of a semiconductor memory device
US5491103A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1994 |
| Grant date | Feb 13, 1996 |
| Priority date | — |
| Expiry date | Apr 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A method for manufacturing a capacitor structure of a highly integrated semiconductor memory device. A first conductive layer is formed on a semiconductor substrate, and a first pattern is formed on the first conductive layer. A first material layer is formed on the resultant structure whereon the first pattern is formed, and the first material layer is etched anisotropically, to thereby form a spacer on the side of the first pattern. After etching the first conductive layer using the spacer as an etch-mask, the first pattern is removed. A second conductive layer is formed on the resultant structure and etched anisotropically. The spacer is removed, to thereby form a storage electrode of a capacitor. The distance between neighboring capacitors can be minimized to a value smaller than the limitation imposed by the lithographic technique, to thereby maximize the area of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.