Circuit and method of differential amplitude detection
US5491434A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1994 |
| Grant date | Feb 13, 1996 |
| Priority date | — |
| Expiry date | Dec 5, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/10
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V.sub.OUT that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V.sub.OUT signal for providing an error free true data output signal VTO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.