Compensated CMOS driver circuit with reduced DC losses
US5491436A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 1994 |
| Grant date | Feb 13, 1996 |
| Priority date | — |
| Expiry date | Jul 29, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to the present invention, an improved integrated circuit is provided having a first, second and third FET device and wherein at least one performance characteristic of the first and second device varies in the same manner with the variations of one performance related process variable condition such that each of the first and second devices have an output signal changed by a change in that performance related variable condition, and the first and second devices are connected with the one output characteristic of the second device acting in opposition to that of the first device to provide a merged output signal representative of offsetting effects of the first and second devices. The third device is connected within a voltage divider and coupled to the first and second FET devices to turn off both the divider and the second device responsive to the merged output signal rising to a select value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.